The invention concerns CMOS integration technology (Complementary Metal Oxide Semiconductor) using a family of electronic components with low electric consumption. The invention particularly concerns CMOS pixel structures and image sensor arrays incorporating the same.
CMOS integration technology allows the production of chips for monolithic cameras having good resolution and reasonable image quality. The application of these techniques also allows the obtaining of sensors with low energy consumption. Such sensors also offer fast reading speed on account of the very good operating dynamics of CMOS pixels through the rapid switching of CMOS transistors. In addition, these technologies offer the possibility of integrating packaging, processing, coding and communication functions.
FIG. 1 illustrates the structure of a pixel of an active pixel sensor (APS) having three transistors. Said pixel comprises:                a P-type semiconductor substrate 1;        a photoelectric conversion zone NPD defined by N-doping in the substrate 1 and accumulating an amount of charge during exposure to light, the PN junction formed by the photoelectric conversion zone NPD and the substrate 1 forming a photodiode;        an insulating layer 2 of silicon dioxide on the surface of the substrate 1;        a readout circuit to read a voltage variation induced by charge accumulation, said readout circuit comprising:                    a reset transistor T1 controlled by a reset signal RST on its gate for pre-charge resetting of the voltage of the photodiode, said reset transistor T1 having an electrode connected to the photoelectric conversion zone NPD and another electrode connected to the voltage supply VDD;            a readout transistor T2 whose gate is connected to the photoelectric conversion zone NPD whilst one of its electrodes is connected to the voltage supply VDD;            a select transistor T3 controlled by a selection signal SEL which can be applied to its gate, one of its electrodes being common with the other electrode of the readout transistor T2 and the other being connected to a readout line COL.                        
The photoelectric charge is therefore self-integrated on the junction capacitance of the photodiode after the pre-charge action of the reset transistor T1, and is then read via switching of the select transistor T3. The readout sequence is illustrated in FIG. 2 which gives an operating chronogram of the three-transistor active CMOS pixel shown in FIG. 1.
In this chronogram are schematically illustrated in arbitrary value as a function of time: the course 21 of the reset signal RST, the course 22 of the select signal SEL, the course 23 of voltage VNPD at the photoelectric conversion zone NPD and the course 24 of voltage VCOL on the readout line COL.
At time t1, the photodiode is reset, before imaging, at an initial voltage by means of a reset signal RST activating the reset transistor T1. At time t2 the reset transistor T1 is de-activated by the RST signal and an initial readout then allows determination of said initial voltage to cancel the shift of a voltage follower in the readout circuit. At time t3 the select transistor T3 is deactivated by means of the select signal SEL to allow the photodiode to develop under illumination during exposure. Finally, at time t4 the final readout is performed at the end of exposure by means of a select signal SEL to collect the voltage representing illumination. The final output signal is the difference between the final readout and the initial readout.
However the charge-voltage conversion factor is low on account of the strong value of the junction capacitor forming the photodiode. In addition, during reset readout after time t3, there occurs a switching noise KTC perturbing proper readout of the initial voltage and which cannot be compensated. This structure additionally has a strong dark current in the photodiode on account of surface contact between the silicon of the substrate 1 and the layer of silicon dioxide 2.
One solution to these problems is to transfer the photoelectric charge accumulated in the photodiode onto a small capacitor for charge-voltage conversion. In this case a large photodiode allows the collecting of more photoelectric charge and a small conversion capacitor allows a signal with more ample voltage. For example one electron generates a voltage of 16 μV on a capacitor of 10 fF, but on a capacitor of 1 fF it will generate 160 μV. A strong conversion factor allows system noise to be overcome more easily and improves the detection limit of a pixel.
This solution is implanted in a so-called four-transistor active pixel structure as shown in FIG. 3. The readout circuit is similar to that of the three-transistor active pixel previously described with the difference that here it is connected to a node called a floating diffusion node FD. This floating diffusion node FD is defined by N-doping in the substrate 1. This floating diffusion node FD is therefore a small capacitor formed of a small-sized PN junction. The low capacitance value of the floating diffusion node FD causes a large variation in voltage when an electric charge is transferred thereto.
The pixel also comprises a photoelectric conversion zone NPD defined by N-doping in the substrate 1 and accumulating a photoelectric charge during exposure to light. Here it comprises a P-doped surface zone PIN to isolate the photoelectric conversion zone NPD from the isolating layer 2 of silicon dioxide. This heavily P-doped surface zone PIN on the upper surface of the photoelectric conversion zone NPD, connected to the substrate 1 (here acting as ground) suppresses the strong dark current generated on the surface of the silicon substrate 1. This photodiode structure is called a <<pinned photodiode>> (PPD) since the surface potential is pinned at a fixed potential.
A transfer transistor TX transfers the photoelectric charge of the photoelectric conversion zone NPD towards the floating diffusion node FD. For this purpose, the N-doping of said floating diffusion node FD is heavier than the N-doping of the photoelectric conversion zone NPD. In general, the transfer transistor TX is formed by a MOS transistor with surface channel where the heavily P-doped surface zone PIN and the photoelectric conversion zone NPD are aligned with one of the edges of the gate TX.
When the gate of the transfer transistor TX is biased with a low potential, an electric barrier is formed between the floating diffusion node FD and the photoelectric conversion zone NPD. The photoelectric conversion zone NPD is then in an integration state. The electric potential of the photoelectric conversion zone NPD of the photodiode PPD must also fully deplete the latter of free electrons so that only pinned positive charges remain in the photoelectric conversion zone NPD at the start of exposure.
When the gate of the transfer transistor TX is biased with a high potential, this electric barrier is lowered, then allowing the photoelectric charge to pass from the photoelectric conversion zone NPD towards the floating diffusion node FD. The variation in voltage on the floating diffusion node FD generates a voltage signal proportional to the amount of charge received.
The variation in voltage is measured by the readout circuits composed of a voltage follower within the pixel and differential amplifiers on the periphery of the pixel array. Voltage variation measurement is based on two correlated readouts therefore allowing suppression of reset noise.
FIG. 4 is a chronogram of the four-transistor active pixel. This chronogram schematically illustrates in arbitrary units as a function of time: the course 41 of the reset signal RST, the course 42 of the signal applied to the gate of the transfer transistor TX, the course 43 of the select signal SEL, the course 44 of voltage VFD at the floating diffusion node FD and the course 45 of voltage VCOL on the readout line COL. At time t1 the floating diffusion node FD is reset, before image-taking, at an initial voltage by means of the RST signal activating the reset transistor T1, and the select transistor T3 becomes conductive by means of the select signal SEL.
At time t2 the reset transistor T1 is deactivated and initial readout allows determination of said initial voltage. At time t3 the transfer transistor TX is made conductive to transfer the charges from the photoelectric conversion zone NPD towards the floating diffusion node FD. At time t4 the transfer transistor TX is deactivated whilst a second readout takes place on the readout line. At time t5 the select transistor T3 is deactivated.
The output signal is the difference between the initial readout and the second readout, and is formed by the variation in voltage caused by the photoelectric charge accumulated in the photoelectric conversion zone NPD which has been transferred to the floating diffusion node FD. The reset noise of the floating node FD is therefore naturally compensated by the differential readout circuit.
In prior art embodiments, it is typically sought to obtain the best possible alignment between the heavily P-doped surface zone PIN, the photoelectric conversion zone NPD and the edge of the gate of the transfer transistor TX. The heavily P-doped surface zone PIN must effectively insulate the photoelectric conversion zone NPD from the silicon surface 2 since any contact between the photoelectric conversion zone NPD and an exposed part of the silicon surface 2 would generate a strong dark current.
It is then typically sought to ensure that this alignment forms neither a barrier nor an energy pocket for charge transfer. A parasitic barrier prevents complete transfer of charges from the photoelectric conversion zone NPD towards the floating diffusion node FD. Incomplete charge transfer creates readout noise and pixel afterglow. An energy pocket may retain part of the charges during transfer and will cause the same problems of noise and pixel afterglow.
FIGS. 5a, 5b and 5c show an example of the consequence of misalignment in the PPD photodiode and gate of the transfer transistor TX wherein the photoelectric conversion zone NPD does not extend as far as the gate of the transfer transistor TX.
FIG. 5a shows a cross-section of the pixel structure in FIG. 3, and FIGS. 5b and 5c schematically illustrate the energy levels of the electrons in the corresponding regions when the gate of the transfer transistor TX is biased with a low potential and a high potential respectively.
When the gate of the transfer transistor TX is biased with a low potential (FIG. 5b) the corresponding energy level 51 of the electrons is high containing the charge in the photoelectric conversion zone NPD.
When the gate of the transfer transistor TX is biased with a high potential (FIG. 5c) it can be seen that, since the photoelectric conversion zone does not extend as far as the gate of the transfer transistor TX, an electric barrier 53 at missing part 54 of the photoelectric conversion zone NPD prevents the transfer of charges 55 from the photoelectric conversion zone NPD towards the low energy level 52 created by applying a high potential to the transfer transistor TX, and hence towards the floating diffusion node FD.
FIGS. 6a, 6b and 6c give an example of the consequences of misalignment in the photodiode PPD and gate of the transfer transistor TX wherein the heavily P-doped surface zone PIN does not extend as far as the gate of the transfer transistor TX and therefore leaves part 64 of the photoelectric conversion zone in contact with the insulating layer 2, setting up a large dark current.
FIG. 6a is a cross-section of the pixel structure in FIG. 3, and FIGS. 6b and 6c schematically illustrate the energy levels of the electrons in the corresponding regions when the gate of the transfer transistor TX is biased with a low potential and a high potential respectively.
When the gate of the transfer transistor TX is biased with a low potential (FIG. 6b) the corresponding electron energy level 61 is high, containing the charge in the photoelectric conversion zone NPD.
When the gate of the transfer transistor TX is biased with a high potential (FIG. 6c) it can be seen that the part 64 of the photoelectric conversion zone in contact with the insulating layer 2 results in the onset of an energy pocket 63 wherein the electron energy level is lower than the energy level 62 corresponding to the application of a high potential to the gate of the transistor TX.
The transfer of charges 65 accumulated in the photoelectric conversion zone NPD is therefore only partial. If one part 66 of the charge is indeed transferred towards the floating diffusion node FD, another part 67 of the charge remains trapped at the energy well 67.
In addition, in this structure of a four-transistor pixel the coupling between the photoelectric conversion zone NPD and the gate of the transfer transistor TX forms another difficulty. A photodiode PPD is a buried device wherein the charge is stored in the bulk of the silicon. The gate of the transfer transistor TX is a surface device wherein the charge transfer channel 80, transferring charges in the accumulation region 81 of the photoelectric conversion zone NPD from the latter towards the floating diffusion node FD, is located on the surface of the silicon as illustrated in FIG. 7. The arrow in FIG. 7 shows the charge transfer pathway under the gate of the transfer transistor TX. Much engineering endeavour is required to ensure the transition between the buried accumulation region 81 in the photoelectric conversion zone NPD and the surface transfer channel 80 underneath the gate TX.
The fact that the transfer transistor TX acts as surface device raises a possible problem of dark current for the photodiode PPD. The generation of electron-hole pairs under the gate of the transfer transistor TX may propagate within the photodiode PPD contaminating the latter. Great care must be given to all fabrication steps.
This structure with photodiode PPD and charge transfer transistor TX is similar to the structure of a virtual phase Charge Coupled Device CCD disclosed in U.S. Pat. No. 4,779,124. These problems are analysed in U.S. Pat. No. 5,077,592 and an improved so-called OPP structure (Open Pinned Phase) is proposed.
U.S. Pat. No. 6,221,686 proposes forming the basic structure of a four-transistor active pixel in a standard CMOS structure. U.S. Pat. No. 6,979,587 provides an improvement in the positioning of the photoelectric conversion zone NPD in relation to the isolating islands STI.
U.S. Pat. No. 5,880,495 and U.S. Pat. No. 5,903,021 improve on the transition between the photoelectric conversion zone PPD and the gate of the transfer transistor TX by adding N-type diffusion around the boundaries between the photoelectric conversion zone PPD and the gate of the transfer transistor TX.
U.S. Pat. No. 6,100,551 proposes diffusion underneath the gate of the transfer transistor TX. This diffusion allows the formation of a buried channel. However the structure remains vulnerable to misalignment of masks during fabrication of the pixel structure.
U.S. Pat. No. 6,900,484, U.S. Pat. No. 7,378,696, U.S. Pat. No. 7,388,241, U.S. Pat. No. 7,432,543 and U.S. Pat. No. 7,618,839 propose the creation of a highly sophisticated doping profile in the bulk of the substrate silicon for the photoelectric conversion zone NPD to obtain better transfer of charges from the latter to the diffusion node FD. U.S. Pat. No. 7,898,101 proposes replacing the highly doped surface layer PIN by a biased transparent electrode to bypass the aligning constraint between the highly doped surface layer PIN, the photoelectric conversion zone NPD and the gate of the transfer transistor TX.
The fabrication of a four-transistor active CMOS pixel therefore remains highly complex and costly despite it conceptual simplicity. Very few CMOS foundries can master these techniques.
It follows in particular from the foregoing that persons skilled in the art have always sought to align the gate of the transfer transistor TX with the doped regions forming the photodiode PPD. This alignment is generally obtained by forming said gate of the transfer transistor TX before implanting the doped regions forming the photodiode PPD, the gate of the transfer transistor TX then acting as mask for the implanting of the doped regions forming the photodiode PPD.
In CMOS technology fabrication processes, miniaturisation of the transistors is of importance. One major difficulty encountered is the diffusion of dopants during fabrication. For good dopant activation after ion implantation, ultra-short heat treatments at high temperature (Rapid Thermal Annealing—RTA) are used for the purpose of obtaining maximum limitation of dopant diffusion. RTA can obtain efficient activation of dopants and limit the diffusion thereof since the diffusion rate of dopants is scarcely temperature-dependent.
However this type of fabrication is not optimal for image sensors in which good quality PN junctions are needed for the photodiode. Therefore in the first embodiment presented below the photodiode junctions can only be formed using the same heat treatment as for the CMOS transistors.